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ds07-16202-2e fujitsu semiconductor data sheet 32-bit proprietary microcontroller cmos fr family mb91191/192 series mb91191r/mb91192/mb91f191a/mb91f192 n n n n description the mb91191/192 series is a single-chip microcontroller using a 32-bit risc-cpu (fr series) as its core. it contains peripheral i/o resources suitable for software servo control in applications such as vtrs that require high-speed cpu processing. n n n n features cpu ? 32-bit risc (fr series) , load/store architecture, 5-stage pipeline ? general-purpose registers : 16 32-bit ? 16-bit fixed-length instructions (basic instructions) , 1 instruction per cycle ? includes memory-to-memory transfer, bit manipulation, and barrel shift instructions : optimized for embedded applications ? includes function entry/exit instructions and multiple-register load/store instructions : instruction set supports high level languages ? register interlock function : for efficient assembly language coding ? branch instructions with delay slots : reduced overhead for branch operations ? internal multiplier unit is supported at instruction level signed 32-bit multiplication : 5 cycles signed 16-bit multiplication : 3 cycles ? interrupts (pc and ps saving) : 6 cycles, 16 priority levels (continued) n n n n pac k ag e plastic, lqfp, 120-pin (fpt-120p-m05) plastic, flga, 144-pin (lga-144p-m02)
mb 91191/192 series 2 bus interface ? 16-bit address output, 8/16-bit data input and output ? basic bus cycle : 2 clock cycles ? supports interfaces for various types of memory ? multiplexed data/address input/output ? automatic wait cycles : between 0 and 7 wait cycles can be specified independently for each memory area ? unused data/address pins can be configured as input/output ports ? supports little endian mode bit search module ? searches, starting from the msb, for the position of the first 1/0 bit transition in a word. the operation is performed in one cycle. serial i/o ? 3 channels with internal buffer ram (automatic transfer of up to 128 bytes) ? independent send and receive buffer mode (automatic transfer of up to 64 bytes) a/d converter (successive approximation type) ? 10-bit 16 channels ? uses successive approximation conversion method (conversion time : 8.4 m s @ 20 mhz) ? channel scan function ? hardware and software conversion start functions ? internal fifo (software conversion : 6 stages, hardware conversion : 6 stages) timers ? 16-bit 4 channels ? 16-bit timer/counter 1 channel (with square wave output) ? 8/16-bit timer/counter 1 channel (with square wave output) fg input unit ? incorporates capstan, drum, and reel input circuits capture unit ? internal 24-bit free-run counter (minimum resolution = 50 ns @ 20 mhz) ? internal fifo (data : 21-bit 8, detection : 8-bit 8) programmable pattern generator ? internal ram buffer (ppg0 : 256 bytes, ppg1 : 64 bytes) ? output timing resolution : 800 ns @ 20 mhz ? includes an a/d converter hardware start function realtime timing generator ? rtg : 3 circuits ? output timing resolution : 400 ns or 800 ns selectable ? timing output ports : 5 ports pwm ? 12-bit pwm 6 channels (rate, multi-type) ? base frequency = 78.1 khz or 39.0 khz (@ 20 mhz) selectable (continued)
mb 91191/192 series 3 (continued) pwc ?8-bit pwc 1 channel (with mask input) ? measurement resolution : 400 ns @ 20 mhz general-purpose prescaler ? 10-bit prescaler 1 channel (with square wave and pulse outputs) ? dedicated internal oscillator circuit ? includes load function driven by ppg output interrupt control ? external interrupts : 3 inputs ? key input interrupt : 8 inputs
mb 91191/192 series 4 n n n n pin assignment (continued) pa0/an-8/key0 pb7/an-7 pb6/an-6 pb5/an-5 pb4/an-4 pb3/an-3 pb2/an-2 pb1/an-1 pb0/an-0 av dd av rh av ss v ss p17/rtg4 p16/rtg3 p15/rtg2 p14/rtg1 p13/rtg0 p12/ec5/int1 p11/ec4/int0 p10/pmsk p07/exi2/pmi p06/exi1 p05/exi0 p04/cfg p03/dfg p02/dpg p01/rfg0 p00/rfg1 v dd p93/ppg02 p94/ppg03 p80/ppg04 p81/ppg05 p82/ppg06 p83/ppg07 p84/ppg08 p85/ppg09 p86/ppg10 p87/ppg11 p40/ppg12 p41/ppg13 p42/ppg14 p43/ppg15 p44/ppg16 p45/ppg17 p46/ppg18 p47 p57 p56 p55 p54 p53 p52 p51 p50 v ss p37 p36 p35 a15 a14 a13 a12 a11 a10 a09 a08 d31/a07 d30/a06 d29/a05 p57 p56 p55 p54 p53 p52 p51 p50 d31/a15 d30/a14 d29/a13 pa1/an-9/key1 pa2/an-a/key2 pa3/an-b/key3 pa4/an-c/key4 pa5/an-d/key5 pa6/an-e/key6 pa7/an-f/key7 pd0/si2 pd1/so2 pd2/sck2 pd3/si1/int2 pd4/so1 pd5/sck1 pd6/scs0 pd7/si0 pc0/so0 pc1/sck0 pc2/pwm5/scs1 pc3/pwm4/scs2 pc4/pwm3 pc5/pwm2 pc6/pwm1 pc7/pwm0 v ss osci/pck osco v dd p90/p0 p91/ppg00 p92/ppg01 ale wr1 wr0 rd a00/d16 a01/d17 a02/d18 a03/d19 a04/d20 a05/d21 a06/d22 a07/d23 a08/d24 a09/d25 a10/d26 a11/d27 a12/d28 ale p62 wr0 rd p20 p21 p22 p23 p24 p25 p26 p27 a00/d24 a01/d25 a02/d26 a03/d27 a04/d28 x0 x1 v ss md2 md1 md0 rst p70/xout p67/t40 p66/t501 p65 p64 p63 p62 p61 p60 p20 p21 p22 p23 p24 p25 p26 p27 v dd p30 p31 p32 p33 p34 16-bit mpx mode 8-bit mpx mode 95 100 105 110 115 120 90 85 80 75 70 65 5 10 15 20 25 30 60 55 50 45 40 35 (top view) (fpt-120p-m05)
mb 91191/192 series 5 (continued) top view 65 osco 66 osci 30 p34 28 p32 29 p33 64 v dd 68 pc7 69 pc6 27 p31 25 v dd 26 p30 67 v ss 71 pc4 72 pc3 24 p27 22 p25 23 p26 70 pc5 74 pc1 75 pc0 21 p24 19 p22 20 p23 73 pc2 77 pd6 76 pd7 18 p21 16 p60 17 p20 78 pd5 80 pd3 79 pd4 13 p63 15 p61 14 p62 81 pd2 83 pd0 82 pd1 10 p66 12 p64 11 p65 84 pa 7 86 pa 5 85 pa 6 7 rst 9 p67 8 p70 87 pa 4 89 pa 2 88 pa 3 4 md2 6 md0 5 md1 90 pa 1 32 p36 59 p94 56 p82 53 p85 50 p40 47 p43 44 p46 41 p56 38 p53 35 p50 33 p37 58 p80 55 p83 52 p86 49 p41 46 p44 45 p45 42 p57 39 p54 36 p51 62 p91 63 p90 31 p35 61 p92 60 p93 57 p81 54 p84 51 p87 48 p42 43 p47 40 p55 37 p52 34 v ss 1 x0 3 v ss 2 x1 91 pa 0 94 pb5 97 pb2 100 av dd 103 v ss 108 p13 111 p10 114 p05 117 p02 120 v dd 93 pb6 96 pb3 99 pb0 102 av ss 105 p16 106 p15 109 p12 112 p07 115 p04 118 p01 92 pb7 95 pb4 98 pb1 101 av rh 104 p17 107 p14 110 p11 113 p06 116 p03 119 p00 (lga-144p-m02) note : the flga-144 package is not supplied for the mb91191 series. it is supplied only for the mb91192 series.
mb 91191/192 series 6 n n n n pin descriptions (continued) pin no. pin name circuit type function 1 x0 (i) a crystal oscillator pins 2 x1 (o) 3v ss ? v ss pin 4md2 b operation mode setting pins cmos schmitt inputs 5md1 6md0 7rst b reset input pin. cmos schmitt input. 8 p70/xout c shared pin with clock output (x0/2, pck/2) . cmos input. 9 p67/t40 c shared pin with timer 4 square wave output. cmos input. 10 p66/t501 shared pin with timer 5 square wave output. cmos input. 11 p65 general-purpose i/o port. cmos input. 12 p64 general-purpose i/o port. cmos input. 13 p63/ale/ale shared pin with address strobe output. cmos input. 14 p62/p62/wr1 shared pin with write strobe output 1. cmos input. 15 p61/wr0 /wr0 shared pin with write strobe output 0. cmos input. 16 p60/rd /rd shared pin with read strobe output. cmos input. 17 p20/p20/d16 : a00 c general-purpose i/o ports. cmos inputs. 18 p21/p21/d17 : a01 19 p22/p22/d18 : a02 20 p23/p23/d19 : a03 21 p24/p24/d20 : a04 22 p25/p25/d21 : a05 23 p26/p26/d22 : a06 24 p27/p27/d23 : a07 25 v dd ? power supply pin 26 p30/d24 : a00/d24 : a08 c shared external bus pins and high-current i/o ports. cmos inputs. 27 p31/d25 : a01/d25 : a09 28 p32/d26 : a02/d26 : a10 29 p33/d27 : a03/d27 : a11 30 p34/d28 : a04/d28 : a12 31 p35/d29 : a05/d29 : a13 32 p36/d30 : a06/d30 : a14 33 p37/d31 : a07/d31 : a15 34 v ss ? v ss pin
mb 91191/192 series 7 (continued) pin no. pin name circuit type function 35 p50/a08/p50 c shared external bus pins and high-current i/o ports. cmos inputs. 36 p51/a09/p51 37 p52/a10/p52 38 p53/a11/p53 39 p54/a12/p54 40 p55/a13/p55 41 p56/a14/p56 42 p57/a15/p57 43 p47 c general-purpose i/o port. cmos input. 44 p46/ppg18 shared pins with ppg outputs. cmos inputs. 45 p45/ppg17 46 p44/ppg16 47 p43/ppg15 48 p42/ppg14 49 p41/ppg13 50 p40/ppg12 51 p87/ppg11 c shared pins with ppg outputs. cmos inputs. 52 p86/ppg10 53 p85/ppg09 54 p84/ppg08 55 p83/ppg07 56 p82/ppg06 57 p81/ppg05 58 p80/ppg04 59 p94/ppg03 c shared pins with ppg outputs. cmos inputs. 60 p93/ppg02 61 p92/ppg01 c shared pins with ppg outputs. cmos inputs. 62 p91/ppg00 63 p90/p0 shared pin with general-purpose prescaler output. cmos input. 64 v dd ? power supply pin 65 osco (o) a crystal oscillator pins for dedicated general-purpose prescaler oscillation. 66 osci/pck (i) 67 v ss ? v ss pin
mb 91191/192 series 8 (continued) pin no. pin name circuit type function 68 pc7/pwm0 c shared pins with pwm outputs. cmos inputs. 69 pc6/pwm1 70 pc5/pwm2 71 pc4/pwm3 72 pc3/pwm4/scs2 f shared pin with pwm output and serial 2 chip select. cmos schmitt input. 73 pc2/pwm5/scs1 shared pin with pwm output and serial 1 chip select. cmos schmitt input. 74 pc1/sck0 shared pin with serial 0 shift clock. cmos schmitt input. 75 pc0/so0 c shared pin with serial 0 serial output. cmos input. 76 pd7/si0 f shared pin with serial 0 serial input. cmos schmitt input. 77 pd6/scs0 shared pin with serial 0 chip select input. cmos schmitt input. 78 pd5/sck1 shared pin with serial 1 shift clock. cmos schmitt input. 79 pd4/so1 c shared pin with serial 1 serial output. cmos input. 80 pd3/si1/int2 f shared pin with serial 1 serial input and external interrupt 2. cmos schmitt input. 81 pd2/sck2 shared pin with serial 2 shift clock. cmos schmitt input. 82 pd1/so2 c shared pin with serial 2 serial output. cmos input. 83 pd0/si2 f shared pin with serial 2 serial input. cmos schmitt input. 84 pa7/an-f/key7 e shared pins with analog inputs and key inputs. cmos schmitt inputs 85 pa6/an-e/key6 86 pa5/an-d/key5 87 pa4/an-c/key4 88 pa3/an-b/key3 89 pa2/an-a/key2 90 pa1/an-9/key1 91 pa0/an-8/key0
mb 91191/192 series 9 (continued) pin no. pin name circuit type function 92 pb7/an-7 d shared pins with analog inputs. cmos schmitt inputs. 93 pb6/an-6 94 pb5/an-5 95 pb4/an-4 96 pb3/an-3 97 pb2/an-2 98 pb1/an-1 99 pb0/an-0 100 av dd ? a/d converter power supply pin 101 av rh ? a/d converter reference power supply pin 102 av ss ? a/d converter v ss pin 103 v ss ? v ss pin 104 p17/rtg4 c shared pins with rtg outputs. cmos inputs. 105 p16/rtg3 106 p15/rtg2 107 p14/rtg1 108 p13/rtg0 109 p12/ec5/int1 f shared pin with timer 5 clock input and external interrupt input. cmos schmitt input. 110 p11/ec4/int0 shared pin with timer 4 clock input and external interrupt input. cmos schmitt input. 111 p10/pmsk shared pin with pwc mask input. cmos schmitt input. 112 p07/exi2/pmi f shared pin with external capture input and pwc input. cmos schmitt input. 113 p06/exi1 shared pin with external capture input. cmos schmitt input. 114 p05/exi0 115 p04/cfg shared pin with capstan fg input. cmos schmitt input. 116 p03/dfg shared pin with drum fg input. cmos schmitt input. 117 p02/dpg shared pin with drum pulse input. cmos schmitt input. 118 p01/rfg0 shared pins with reel fg inputs. cmos schmitt inputs. 119 p00/rfg1 120 v dd ? power supply pin
mb 91191/192 series 10 n n n n i/o circuits (continued) type circuit remarks a ? oscillation feedback resistor : 1 m w approx. b ? cmos schmitt input c ? cmos level output ? cmos input no standby control d ? cmos level output ? cmos input with input control ? analog input x0,osci x1,osco clock input standby control signal input standby control signal = 1 (fixed) output data input dc test dc test input control output data dc test dc test analog input ch selection digital input
mb 91191/192 series 11 (continued) type circuit remarks e ? cmos level output ? cmos schmitt input with input control ? analog input f ? cmos level output ? cmos schmitt input no standby control h ? cmos level output ? cmos schmitt input no standby control input control input data dc test dc test analog input ch selection digital input standby control signal = 1 (fixed) output data input dc test dc test output data input dc test dc test
mb 91191/192 series 12 n n n n block diagram p47 p46/ppg18 p45/ppg17 p44/ppg16 p43/ppg15 p42/ppg14 p41/ppg13 p40/ppg12 p87/ppg11 p86/ppg10 p85/ppg09 p84/ppg08 p83/ppg07 p82/ppg06 p81/ppg05 p80/ppg04 p94/ppg03 p93/ppg02 p92/ppg01 p91/ppg00 p90/p0 pd0/si2 pd1/so2 pd2/sck2 pd3/si1/int2 pd4/so1 pd5/sck1 pd6/scs0 pd7/si0 pc0/s00 pc1/sck0 pc2/pwm5/scs1 pc3/pwm4/scs2 pc4/pwm3 pc5/pwm2 pc6/pwm1 pc7/pwm0 pa7/an-f/key7 pa6/an-e/key6 pa5/an-d/key5 pa4/an-c/key4 pa3/an-b/key3 pa2/an-a/key2 pa1/an-9/key1 pa0/an-8/key0 pb7/an-7 pb6/an-6 pb5/an-5 pb4/an-4 pb3/an-3 pb2/an-2 pb1/an-1 pb0/an-0 md0 md1 md2 rst p37/d31 p30/d24 p27/d23 p20/d16 p57/a15 p50/a08 p60/rd p61/wr0 p62/wr1 p63/ale p64 p65 p66/t501 p67/t40 p17/rtg4 p16/rtg3 p15/rtg2 p14/rtg1 p13/rtg0 p12/ec5/int1 p11/ec4/int0 p10/pmsk p07/exi2/pmi p06/exi1 p05/exi0 p04/cfg p03/dfg p02/dpg p01/rfg0 p00/rfg1 p70/xout x0 x1 osci osco mode control port 2/3 port 5 port 6 port 7 port 1 port 0 osc osc fr20 cpu core i-bus i-bus d-bus d-bus d-bus c-bus ram 2 kb external bus control 16-bit timers 0 to 3 8/16-bit timer 16-bit timer 4 8-bit pwc interrupt controller cfg dfg rfg0 rfg1 c-unit 10-bit programmable prescaler 24-bit frc fifo 29-bit 8 ram 256 byte ppg0 ppg1 ram 64 byte bit search r-bus ram 128 byte serial ch 0 ram 128 byte serial ch 1 ram 128 byte serial ch 2 12-bit pwm00-02 12-bit pwm10-12 external interrupts 16-bit rtg0-2 external interrupts (key inputs) 10-bit a/dc fifo (software) fifo (hardware) port 4 port 8/9 port c/d port a/b int2 to int0 (from port 1, d) rtg4 to rtg0 (to port 1) mb91191r mb91192 mb91f191a mb91f192 :ram 6 kb :ram 8 kb :ram 6 kb :ram 8 kb mb91191r mb91192 mb91f191a mb91f192 :rom 254 kb :rom 384 kb :flash 254 kb :flash 384 kb to to to
mb 91191/192 series 13 (bus names) ? i bus : 16-bit bus for internal instructions. as the fr family of cpus use the harvard architecture, instructions and data use separate buses. a bus converter is connected to the i bus. ? d bus : internal 32-bit data bus. the internal peripherals are connected to the d bus. ? c bus : internal multiplexed bus. connected to the i and d buses via a switch. an external interface module is connected to the c bus. data and instructions are multiplexed on the external data bus. ? r bus : internal 16-bit data bus. the r bus connects to the d bus via an adapter. the i/o, clock oscillator, and interrupt controller are connected to the r bus. as the r bus is only 16 bits wide, address and data are multiplexed on the bus and therefore multiple cycles are required when the cpu accesses these resources.
mb 91191/192 series 14 n n n n memory map i/o area ppg0 data ram area 256 bytes sio0 data ram area 128 bytes ppg1 data ram area 64 bytes i/o area i/o area access inhibited sio1 data ram area 128 bytes sio2 data ram area 128 bytes access inhibited access inhibited reset vector external extended area mb91191r i/o area ppg0 data ram area 256 bytes sio0 data ram area 128 bytes ppg1 data ram area 64 bytes i/o area i/o area access inhibited sio1 data ram area 128 bytes sio2 data ram area 128 bytes access inhibited access inhibited access inhibited reset vector external extended area mb91192 1 kb initial vector area direct access area 00000000 h 000001ff h 00000200 h 000002ff h 00000300 h 0000037f h 00000380 h 000003bf h 000003c0 h 000003ff h 00000400 h 000007ff h 00000800 h 00000fff h 00001000 h 0000107f h 00001080 h 000010ff h 00001100 h 0000e7ff h 0000e800 h 0000ffff h 00010000 h 000bffff h 000c0000 h 000c07ff h 000c0800 h 000ffffb h 000ffffc h 00100000 h ffffffff h 00000000 h 000001ff h 00000200 h 000002ff h 00000300 h 0000037f h 00000380 h 000003bf h 000003c0 h 000003ff h 00000400 h 000007ff h 00000800 h 00000fff h 00001000 h 0000107f h 00001080 h 000010ff h 00001100 h 0000dfff h 0000e000 h 0000ffff h 00010000 h 0007ffff h 00080000 h 000807ff h 00080800 h 0009ffff h 000a0000 h 000ffffb h 000ffffc h 00100000 h ffffffff h internal ram area 6 kbytes internal ram area 8 kbytes internal ram area 2 kbytes internal rom area 384 kbytes internal ram area 2 kbytes internal rom area 254 kbytes to to to to to to to to to to to to to to to to to to to to to to to to to to to to to to to note : the single chip mode does not allow access to the external extended area. for access to the external extended area, use the mode register to select the internal rom external bus mode.
mb 91191/192 series 15 n n n n flash memory map and sector configuration flash memory is address-mapped differently between when accessed from the fr-cpu and when accessed from the rom programmer.* shown below is address mapping at access from the cpu. * : while the on-board flash memory uses the little endian format, the fr-cpu interface circuit converts data into big endian. as this conversion function does not work during access from the rom programmer, address mapping is different from that in cpu mode. msb side 16 bit lsb side 16 bit flash memory area internal ram area status resistor ffffffff h 000fffff h 000c0800 h 000c0000 h 000007c0 h 00000000 h 000fffff h 000f8003 h 000f4003 h 000f0003 h 000e0003 h 000c0803 h sa4 (16 kbyte) sa3 (8 kbyte) sa2 (8 kbyte) sa1 (32 kbyte) sa0 (63 kbyte) sa9 (16 kbyte) sa8 (8 kbyte) sa7 (8 kbyte) sa6 (32 kbyte) sa5 (63 kbyte) 000ffffc h 31 16 15 0 000f8000 h 000f4000 h 000f0000 h 000e0000 h 000c0800 h 000c0801 h 000e0001 h 000f0001 h 000f8001 h 000f4001 h 000ffffd h 000ffffe h 000f8002 h 000f4002 h 000f0002 h 000e0002 h 000c0802 h msb side 16 bit lsb side 16 bit status resistor internal ram area flash memory area ffffffff h 000fffff h 000a0000 h 00080800 h 00080000 h 000007c0 h 00000000 h 000fffff h 000f4003 h 000f0003 h 000e0003 h 000c0003 h 000a0003 h 31 16 15 0 sa5 (16 kbyte) sa4 (8 kbyte) sa3 (8 kbyte) sa2 (32 kbyte) sa1 (64 kbyte) sa0 (64 kbyte) sa11 (16 kbyte) sa10 (8 kbyte) sa9 (8 kbyte) sa8 (32 kbyte) sa7 (64 kbyte) sa6 (64 kbyte) 000ffffc h 000f8000 h 000f4000 h 000f0000 h 000e0000 h 000c0000 h 000a0000 h 000ffffd h 000f8001 h 000f4001 h 000f0001 h 000e0001 h 000c0001 h 000a0001 h 000ffffe h 000f4002 h 000f0002 h 000e0002 h 000c0002 h 000a0002 h 000f8003 h 000f8002 h mb91f191a mb91f192 sector configuration (sa = sector address) memory map sector configuration (sa = sector address) memory map
mb 91191/192 series 16 n n n n electrical characteristics 1. absolute maximum ratings (v ss = av ss = 0 v) *1 : care must be taken that av dd and av rh do not exceed v dd + 0.3 v such as when turning on the device. also care must be taken that av rh does not exceed av dd . *2 : v i and v o may not exceed v dd + 0.3 v. *3 : the maximum output current is the peak value for a single pin. *4 : the average output current is the average current for a single pin over a period of 100 ms. *5 : the total average output current is the average current for all pins over a period of 100 ms. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min max power supply voltage v dd v ss - 0.3 v ss + 3.5 v analog power supply voltage av dd v ss - 0.3 v ss + 3.5 v *1 analog reference voltage av rh v ss - 0.3 v ss + 3.5 v *1 input voltage v i v ss - 0.3 v ss + 3.5 v *2 output voltage v o v ss - 0.3 v ss + 3.5 v *2 l level maximum output current i ol ? 10 ma *3 l level average output current i olav ? 8ma*4 l level total maximum output current s i ol ? 100 ma l level total average output current s i olav ? 50 ma *5 h level maximum output current i oh ?- 10 ma *3 h level average output current i ohav ?- 4ma*4 h level total maximum output current s i oh ?- 50 ma h level total average output current s i ohav ?- 20 ma *5 power consumption p d ? 500 mw operating temperature t a - 20 + 70 c storage temperature tstg - 55 + 150 c
mb 91191/192 series 17 2. recommended operating conditions (v ss = av ss = 0 v) warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min max power supply voltage v dd 2.7 3.3 v normal operation 2.0 3.3 maintaining ram state in stop mode analog power supply voltage av dd v ss - 0.3 v dd + 0.2 v analog reference voltage av rh av ss av dd v operating temperature t a - 20 70 c
mb 91191/192 series 18 3. dc characteristics (v dd = 3.0 v 0.3 v, v ss = av ss = 0 v, t a = - 20 c to + 70 c) *1 : x0, x1, osci, osco *2 : rst , pc3 to pc1, pd6, pd5, pd3, pd2, pa7 to pa0, p12 to p10, p07 to p00, pd7, pd0 *3 : inputs other than *1, *2, md2 to md0 *4 : p07 to p00, p17 to p10, p27 to p20, p47 to p40, p67 to p60, p70, p87 to p80, p94 to p90, pa7 to pa0, pb7 to pb0, pc7 to pc2, pd7, pd6, pd3, pd0 *5 : p37 to p30, p57 to p50 *6 : pd5, pd4, pd2, pd1, pc1, pc0 *7 : operating current for x0 = 20 mhz, osci = v ss (fixed) , all port outputs = low, gear selection : cpu = 10 mhz, peripherals = 20 mhz *8 : operating current in sleep mode for x0 = 20 mhz, osci = v ss (fixed), all port outputs = low, gear selection : cpu = 10 mhz, peripherals = 20 mhz *9 : operating current in stop mode for x0 = 20 mhz, osci = v ss (fixed) , all port outputs = low, gear selection : cpu = 10 mhz, peripherals = 20 mhz parameter symbol pin name condition value unit remarks min typ max h level input voltage v ih *3 ? 0.7 v dd ? v dd + 0.3 v v ihs *1 ? v dd - 0.4 ? v dd + 0.3 v *2 0.8 v dd ? v dd + 0.3 v v ihm md2 to md0 ? v dd ? v dd + 0.3 v l level input voltage v il *3 ? v ss - 0.3 ? 0.2 v dd v v ils *1 ? v ss - 0.3 ? v ss + 0.4 v *2 v ss - 0.3 ? 0.2 v dd v v ilm md2 to md0 ? v ss - 0.3 ? v ss v h level output voltage v oh1 *4 v dd = 3.0 v, i oh = - 4.0 ma 2.4 ?? v mb91f191a 2.4 ?? v mb91191r v oh2 *5, *6 v dd = 3.0 v, i oh = - 8.0 ma 2.4 ?? v mb91f191a 2.4 ?? v mb91191r l level output voltage v ol1 *4 v dd = 3.0 v, i ol = 4.0 ma ?? 0.6 v v ol2 *5, *6 v dd = 3.0 v, i ol = 8.0 ma ?? 0.6 v v ol3 *4, *5, *6 v dd = 3.0 v, i ol = 1.0 ma ?? 0.3 v mb91191r input leak current i li1 *2 v dd = 3.0 v, v ss < v i < v dd ? 1 5 m a i lix x0, osci ? 8 20 m a power supply current i dd v dd v dd = 3.0 v, *7 ? 50.1 60 ma mb91f191a ? 16 25 ma mb91191r i dds v dd = 3.0 v, *8 ? 24 36 ma mb91f191a ? 13 18 ma mb91191r i ddh v dd = 3.0 v, t a = 25 c, *9 ? 1240 m a mb91f191a ? 10 300 m a mb91191r input capacitance c in other than v dd , v ss , av dd , av ss , and av rh ?? 10 ? pf
mb 91191/192 series 19 4. ac characteristics (1) clock timings (v dd = 3.0 v 0.3 v, v ss = av ss = 0 v, t a = - 20 c to + 70 c) * : the frequency fluctuation value is the maximum percentage deviation from the preset center frequency when using the multiplier (when pll is locked) . parameter symbol condition value unit remarks min max clock frequency f c ? 10 20 mhz clock cycle time t c ? 50 100 ns frequency fluctuation* (pll locked) d r ?? 10 % input clock pulse width p wh ? 20 ? ns p wl input clock rise/fall time t cr ?? 8ns t cf internal operating clock frequency cpu f cp when wait controller set to 1 wait cycle 520mhz peripherals f cpp 10 20 mhz internal operating clock cycle time cpu t cp 50 200 ns peripherals t cpp 50 100 ns d f = center frequency f 0 +a -a + - | a | f 0 100 (%) t c p wh t cf p wl t cr frequency (hz) power supply voltage (v) 3.3 2.7 guaranteed operation range f cp f cpp 10 m 20 m
mb 91191/192 series 20 the figure below shows the relationship between the x0 input and the internal clock based on the gcr (gear control register) , chc, cck1, and cck0 bit settings. where t cych is the h level width of the internal clock and t cycl is the l level width. for example, when set to source oscillation 1/2, gear 1/4 and x0 input frequency = 20 mhz : t cyc = 400 ns, t cych = 350 ns, t cycl = 50 ns cck1/0:11 x0 input source oscillation 1 (chc bit in gcr = 0) (a) gear 1 internal clock cck1/0:00 t cyc t cyc t cyc t cyc t cyc t cyc t cyc t cyc (b) gear 1/2 internal clock internal clock internal clock cck1/0:01 (c) gear 1/4 internal clock cck1/0:10 (d) gear 1/8 cck1/0:11 source oscillation 1/2 (chc bit in gcr = 1) (a) gear x 1 internal clock cck1/0:00 (b) gear x 1/2 cck1/0:01 (c) gear x 1/4 internal clock cck1/0:10 (d) gear x 1/8 internal clock
mb 91191/192 series 21 (2) multiplex bus read/write operation (v dd = + 3.0 v 0.3 v, v ss = av ss = 0 v, t a = - 20 c to + 70 c) *1 : when the bus is delayed by automatic wait insertion, add (t cyc number of wait cycles) to this value. *2 : this value is for gear setting = 1 for the value for gear settings 1/2, 1/4, and 1/8, substitute 1/2, 1/4, and 1/8 respectively for n in the formula below. formula : t cych = (1 - n / 2) t cyc t cycl = (n / 2) t cyc parameter symbol pin name condi- tion value unit re- marks min typ max ale pulse width t ehel ale ? t cyc - 10 ?? ns address delay time t ehav a15 to a0 , d31 to d16 ? t cych - 15 t cych t cych + 15 ns *2 address clear time t ehax ? t cycl - 2t cycl t cycl + 10 ns *2 data delay time t eldv d31 to d16 ??? t cycl + 26 ns *2 rd delay time t elrl rd ? t cyc - 11 t cyc t cyc + 11 ns rd pulse width t rlrh ? t cyc - 11 t cyc t cyc + 11 ns *1 wr0 , wr 1 delay time t elwl wr0 , wr1 ? t cyc - 11 t cyc t cyc + 11 ns wr0 , wr1 pulse width t wlwh ? t cyc - 11 t cyc t cyc + 11 ns *1 data setup ? rd - time t dsrh rd , d31 to d16 ? 15 ?? ns rd -? data hold time t rhdx ? 0 ?? ns t wlwh internal clock ale read time d31 to d16 mpx bus rd write time d31 to d16 mpx bus wr0 , wr1 a15 to a08 when not multiplexed t ehel t ehav t elax t dsrh t rhdx t elrl t rlrh t eldv t whdx t elwl
mb 91191/192 series 22 (3) reset input ratings (v dd = 3.0 v 0.3 v, v ss = av ss = 0 v, t a = - 20 c to + 70 c) (4) power-on reset (v dd = 3.0 v 0.3 v, v ss = av ss = 0 v, t a = - 20 c to + 70 c) parameter symbol pin name value unit remarks min max reset input time t rstl rst 5 t cp ? ns paramete symbol pin name value unit remarks min max power supply rise time t r v dd ? 20 ms power supply cutoff time t off 2 ? ms 0.2 v dd rst t rstl v dd t r 2.7 v 0.2 v t off when turning on the power, start with the rst pin in the "l" level state and allow a time of t rstl after reaching the v dd power supply level before changing the pin to the "h" level. v dd 3.0 v 2.0 v v ss v dd rst maintain ram data t rstl recommended rate of voltage rise is 50 mv/ms or less. sudden changes in the power supply voltage may cause a power-on reset. the recommended practice if you wish to change the power supply voltage while the device is operating is to raise the voltage smoothly.
mb 91191/192 series 23 (5) serial i/o (ch0 to 2) (v dd = + 3.0 v 0.3 v, v ss = av ss = 0 v, t a = - 20 c to + 70 c) parameter sym- bol condition value unit remarks min max serial clock cycle time t scyc internal clock 8 t cpp ? ns sck ? so delay time t slov - 10 50 ns valid si ? sck - t ivsh 50 ? ns sck - ? valid si hold time t shix 50 ? ns serial clock h pulse width t shsl external clock 4 t cpp - 10 ? ns serial clock l pulse width t slsh 4 t cpp - 10 ? ns sck ? so delay time t slov 050ns valid si ? sck - t ivsh 50 ? ns sck - ? valid si hold time t shix 50 ? ns serial busy time t busy ? 6 t cpp ns scs ? sck, so delay time t clzo ? 50 ns scs ? sck input mask time t clsl ? 3 t cpp ns scs ? sck, so hi-z time t choz ? 50 ? ns t scyc sck t slov so si t ivsh t shix t clsl t clzo t slsh t slov t shsl t busy t choz sck so si t ivsh t shix scs ? internal shift clock mode ? external shift clock mode
mb 91191/192 series 24 (6) fg pulse input (v dd = 3.0 v 0.3 v, v ss = av ss = 0 v, t a = - 20 c to + 70 c) note : t c is the clock cycle time of the x0 and x1 pin oscillation. (7) timer external clock input (v dd = + 3.0 v 0.3 v, v ss = av ss = 0 v, t a = - 20 c to + 70 c) parameter symbol pin name value unit remarks min max servo input h pulse width t spwh cfg, dfg, dpg, rfg0, rfg1, exi0 to exi2 t c + 50 ? ns servo input l pulse width t spwl t c + 50 ? ns parameter symbol pin name value unit remarks min max timer 4 input h pulse width t ecwh ec4 4 t c + 50 ? ns timer 4 input l pulse width t ecwl 4 t c + 50 ? ns timer 5 input h pulse width t ecwh ec5 4 t cpp ? ns timer 5 input l pulse width t ecwl 4 t cpp ? ns cfg dfg, dpg rfg0, rfg1 exi0 to exi2 t spwh t f t spwl t r ec4, ec5 t r t ecwh t f t ecwl
mb 91191/192 series 25 (8) general-purpose prescaler (v dd = 3.0 v 0.3 v, v ss = av ss = 0 v, t a = - 20 c to + 70 c) parameter symbol pin name value unit remarks min max pck input clock frequency f cp pck ? 12 mhz pck input h pulse width t spwh 33 ? ns pck input l pulse width t spwl 33 ? ns pck input fall time t f pck ? 100 ns rise time t r po output delay time t popi po ? 80 ns pck po t spwh t f t spwl t r t popi
mb 91191/192 series 26 5. electrical characteristics for the a/d converter (v dd = 3.0 v + 0.3 v, v ss = av ss = 0 v, t a = - 20 c to + 70 c) notes : the relative error increases as |av rh | becomes smaller. ensure that the output impedance of the external circuit connected to the analog input meets the following condition : output impedance of external circuit < 7 k w (approx.) if the output impedance of the external circuit is too high, the analog voltage sampling time may be too short. (sampling time = 6.4 m s for a 20 mhz machine clock) parameter symbol pin name condition value unit remarks min typ max resolution ?? ? ? ? 10 bit conversion time ?? ? 8.4 ??m s total error ?? v dd = av dd = 3.0 v, av rh = 3.0 v ?? 4.0 lsb linearity error ?? ? ? 3.5 lsb differential linearity error ?? ? ? 2.0 lsb zero transition error v ot an-0 to an-f v dd = av dd = 3.0 v, av rh = 3.0 v av ss - 1.5 av ss + 0.5 av ss + 2.5 lsb full-scale transition error v fst an-0 to an-f av rh - 5.5 av rh - 1.5 av rh + 0.5 lsb analog input current i ain an-0 to an-f ?? 0.1 10 m a analog input voltage v ain an-0 to an-f ? av ss ? av rh v reference voltage av rh av rh ??? av dd v power supply current during conversion i a av dd v dd = av dd = 3.0 v ? 3.0 ? ma conver- sion halted i ah ?? 5.0 m a reference voltage supply current during conversion i r av rh v dd = av dd = 3.0 v, av rh = 3.0 v ? 100 ?m a conver- sion halted i rh ?? 10 m a variation between channels ? an-0 to an-f ??? 4lsb
mb 91191/192 series 27 6. flash memory erase and programming performance parameter condition value unit remarks min typ max sector erase time t a = + 25 c , v cc = 3.0 v ? 115s excludes 00h programming prior erasure chip erase time ? 10 ? s mb91f191a excludes 00h programming prior erasure ? 12 ? mb91f192 half word (16 bit width) programming time ? 16 3,600 m s excludes system-level overhead erase/program cycle ? 10,000 ?? cycle data holding time ? 100 , 000 ?? h
mb 91191/192 series 28 7. a/d converter glossary ? resolution : the change in analog voltage that can be recognized by the a/d converter. ? linearity error the deviation between the actual conversion characteristics and the line linking the zero transition point (00 0000 0000 b ?? 00 0000 0001 b ) and the full scale transition point (11 1111 1110 b ?? 11 1111 1111 b ) . ? differential linearity error the variation from the ideal input voltage required to change the output code by 1 lsb. ? total error the total error is the difference between the actual value and the theoretical value. includes the zero transition error, full-scale transition error and linearity error. 1 lsb (theoretical) = [v] total error for digital output n = v ot (theoretical) = av ss + 0.5 lsb [v] v fst (theoretical) = av rh - 1.5 lsb [v] v nt : voltage at which digital output changes from (n + 1) to n av rh - av ss 1024 v nt - {1 lsb (n - 1) + 0.5 lsb} 1 lsb 1.5 lsb digital output 3ff 3fe 3fd 004 003 002 001 av ss 0.5 lsb theoretical characteristic actual conversion characteristic {1 lsb (n - 1) + 0.5 lsb} actual conversion characteristic total error av rh analog input v nt (measured value)
mb 91191/192 series 29 = [lsb] v ot (theoretical) = [v] v ot : voltage at which digital output changes from (000) h to (001) h . v fst : voltage at which digital output changes from (3fe) h to (3ff) h . v fst - v ot 1022 = - 1 lsb [lsb] v (n+1) t - v nt 1 lsb differential linearity error for digital output n v nt - {1 lsb (n - 1) + v ot } 1 lsb linearity error for digital output n digital output digital output analog input linearity error av ss av rh analog input av ss av rh v ot (measured value) theoretical characteristic actual conversion characteristic v nt (measured value) {1 lsb (n - 1) + vo t } actual conversion characteristic 3ff 3fe 3fd 004 003 002 001 differential linearity error actual conversion characteristic v nt (measured value) actual conversion characteristic theoretical characteristic n + 1 n n - 1 n - 2 v fst (measured value) v fst (measured value)
mb 91191/192 series 30 n n n n ordering infomation part no. package remarks mb91191rpff mb91192pff MB91F191APFF mb91f192pff plastic lqfp, 120-pin (fpt-120p-m05) mb91192lga mb91f192lga plastic flga, 144-pin (lga-144p-m02)
mb 91191/192 series 31 n n n n package dimension (continued) plastic lqfp, 120-pin (fpt-120p-m05) note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches). c 2003 fujitsu limited f120006s-c-4-5 0.07(.003) m index 16.000.20(.630.008)sq 14.000.10(.551.004)sq 130 31 60 91 120 61 90 lead no. (stand off) 0.100.10 (.004.004) 0.25(.010) (.024.006) 0.600.15 (.020.008) 0.500.20 (mounting height) 0~8 ? details of "a" part 1.50 +0.20 C0.10 +.008 C.004 .059 "a" 0.40(.016) 0.160.03 (.006.001) 0.1450.055 (.006.002) 0.08(.003) *
mb 91191/192 series 32 (continued) plastic flga, 144-pin (lga-144p-m02) dimensions in mm (inches). c 2001 fujitsu limited l144002s-c-1-1 11.000.10 0.08(.003) 0.65(.026)typ index area 9.100.10 a 1 0.45(.018) 0.45(.018) 144-?0.35 (.358.004) 0.08(.003) m (144-?.014) (.433.004) (3-?.018) 3-?0.45 max. 1.40(.055) 11.000.10(.433.004)sq ref 5.175(.204) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 b c d e f g h j k l m n p r 5.175 (.204)
mb 91191/192 series fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third- party?fs intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0302 ? fujitsu limited printed in japan

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